1. Field of the Invention
The present invention relates to a hierarchical time to digital converter, and more particularly, to a hierarchical time to digital converter in which a resolution is increased by stages while a phase is compensated for to implement a high resolution and a wide phase detection range.
2. Description of the Related Art
With development of semiconductor manufacturing process technology, circuit line widths have been reduced, and thus the degree of circuit integration is increasing. In addition, reduction in supplied voltage level is resulting in decrease in power consumption. However, the reduction in circuit line width causes an increase in leakage current and results in deterioration in performance of analog circuits. Therefore, circuit design technology is becoming digitized according to the development of process technology.
Currently, time to digital converters represent the most basic and effective technology for digitizing a circuit. A time to digital converter can be designed using a digital circuit alone. Since the time to digital converter converts a phase difference between clocks into a digital signal, it readily processes an output as a digital signal. Therefore, not only can a time to digital converter be widely used in a clock generator designed using a digital circuit, but it can also be effectively used in some Analog-Digital Converters (ADCs).
A conventional basic time to digital converter may be designed as illustrated in FIG. 1. Referring to FIG. 1, a clock IN1 is sampled by a clock IN2 after a specific delay T caused by delay stages 101_1, 101_2, . . . , 101_N and 101_N+1 having the specific delay T. More specifically, flip-flops 103_1, 103_2, . . . , 103_N and 103_N+1 output signal values of the clock IN1 delayed by the delay stages as output values THR<0>, THR<1>, . . . , THR<N−1> and THR<N> at a rising edge of the clock IN2. Here, the time to digital converter counts a value of 1 among the output values THR<0>, THR<1>, . . . , THR<N−1> and THR<N> of the flip-flops 103_1, 103_2, . . . , 103_N and 103_N+1. The counted number of is a phase difference between the clocks IN1 and IN2. Therefore, a position having the minimum phase difference is found, and the phase difference of the position is output in a digital code. However, the time to digital converter cannot detect a phase difference within the specific delay T. The delay T of the time to digital converter is referred to as a resolution of the time to digital converter, which is determined by a phase difference caused by basic delay circuits of the delay stages. In general, a basic delay circuit is made of two inverters having the minimum delay, and it is impossible to make a time to digital converter having a smaller resolution than that of the basic delay circuit renders.
FIG. 2 is a circuit diagram of a time to digital converter having an improved resolution in comparison with the time to digital converter shown in FIG. 1. Two clocks IN1 and IN2 are input into delay stages having a minute difference and sampled with a delay difference of (τ1-τ2). Thus, a resolution is improved in comparison with that of the time to digital converter of FIG. 1.
However, when the resolution of the conventional time to digital converter increases, a phase detection range is reduced. To solve this problem, more delay stages and sampling circuits are necessary. Consequently, the size of the time to digital converter must be increased in order to satisfy a phase detection range and a resolution simultaneously.